Design Recipes for FPGAs: Using Verilog and VHDL

ALU Functions

251

1-bit adder

The arithmetic ‘heart’ of an ALU is the addition function – the

Adder. This starts form a simple 1 bit adder and is then extended

to multiple bits, to whatever sized of addition function is required

in the ALU. The basic design of a 1-bit adder is to take two logic

inputs (a & b) and produce a sum and carry output according to

the following truth table:

This can be implemented using simple logic with a 2 input AND

gate for the carry, and a 2 input XOR gate for the sum function as

shown in Figure 63.

This function has a carry-out (carry), but no carry-in, so to

extend this to multiple bit addition, we need to implement a car ...