Design Recipes for FPGAs: Using Verilog and VHDL

And the resulting VHDL code would be something like the

following:

for I in samples’right downto 1 loop

samples(I) := samples(I-1);

end loop

samples(0) := input;

sum := to_signed(0,32);

for j in 0 to samples’right loop

sum := sum + (to_signed(coeffs(j),16) *

samples(j));

end loop;

output <= sum(30 downto 15);

wait for 1 us;

This is easily parameterized, modified and clear to understand.

Summary

Behavioral VHDL is a useful technique for both initial design

ideas and also the starting point for an RTL design. It is important

to remember, however, that quite a lot of behavioral VHDL cannot

be synthesized and is therefore purely for conceptual design or use

in test ...