Design Recipes for FPGAs: Using Verilog and VHDL

Memory

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begin

rom16x8: entity work.rom16x8 (example)

port map ( address, data );

end architecture test;

Notice that the IEEE library, std_logic_1164, is required for the

std_logic_vector type and the value of the data will depend on the

address chosen.

Random Access Memory

A DRAM block has a two-dimensional structure of memory that

is divided into a grid structure accessed by a row address and col-

umn address. Note that this is asynchronous and therefore has no

clock. The implication of being asynchronous is that care must be

taken with the timing of the memory access to ensure data integrity

throughout the transfer process.

The VHDL model has a single ...