Design Recipes for FPGAs: Using Verilog and VHDL

architecture simple of Johnson_counter is

begin

process(clk, rst)

variable j_state : std_logic_vector((n-1) downto 0);

begin

if rst= '0' then

j_state:= (others => '0');

elsif rising_edge(clk) then

j_state:= not j_state(0) & j_state(n-1 downto 1);

end if;

q <= j_state;

end process;

end architecture simple;

Notice that the concatenation is now putting the inverse (NOT) of

the least significant bit of the internal state variable (j_state(0))

onto the next state most significant bit, and then shifting the cur-

rent state down by one bit.

It is also worth noting that the counter does not have any check-

ing for the case of an incorrect state. It would be sensible ...