Design Recipes for FPGAs: Using Verilog and VHDL

Memory

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we : OUT std_logic;

wp : OUT std_logic;

busy : IN std_logic;

);

END ENTITY FLASHIF;

A typical architecture for this device could be as follows:

Architecture basic of FLASHIF is

Begin

Process (clk) is

If busy = ‘1’ then

If rising_edge(clk) then

Ce <= en;

Ale <= ‘1’;

Cle < ‘1’;

If read = ‘0’ then

We <= ‘1’;

Re <= ‘1’;

Else

We <= ‘0’;

Re <= ‘0’;

End if;

If prog = ‘0’ then

Wp <= ‘0’;

Else

Wp <= ‘1’;

End if;

End if;

End if;

End process;

End architecture basic;

This is a basic outline for a flash controller and this will obvi-

ously change from device to device.

Summary

This chapter has introduced the important memory types of ROM,

asynchronous RAM, FLASH memory and synchronous ...