Design Recipes for FPGAs: Using Verilog and VHDL

Similarly, for numbers which may be too small, and we can

potentially lose precision, do we simply round up or flag another

loss of precision condition? These are questions that the designer

needs to answer for their application, but for the rest of the chap-

ter a simple approach will be taken that illustrates how the basic

functions operate, and the details of handling these issues will be

left to the reader, unless specifically identified and discussed.

Basic fixed point types

The first task in defining a custom fixed point library, is to spec-

ify a new type for the numbers. The closest similar types in stan-

dard VHDL, that can be synthesized, are ...