Design Recipes for FPGAs: Using Verilog and VHDL

We can then identify each major block that requires an external

interface and add the requisite connection points to the top level

entity. It is worth remembering that at each stage of the design, we

do not need to have every block defined completely to test other

parts of the design. We can use behavioral models or even empty

models to simply ensure that the interfaces are in place and then

replace each empty block with a fully functional one. We can also

start with behavioral models, replace with Register Transfer Level

(RTL) models and finally even replace these with synthesized

ones. Thus a complete system can be tested piece by piece until all