Design Recipes for FPGAs: Using Verilog and VHDL

Design Recipes for FPGAs

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The process then defines a wait statement checking vin for

crossing either of those threshold values:

wait on vin’above(vh), vin’above(vl);

The final part of the process is to add the digital output logic

state dependent on the threshold status of vin:

if vin’above(vh) then

d <= ‘1’ after td;

elsif not vin’above(vl) then

d <= ‘0’ after td;

end if;

The output state (d) is then scheduled after the delay time defined

by td.

The completed architecture is shown below:

architecture simple of comparator is

quantity vin across p to m;

begin

p1 : process

constant vh : real := ABS(hys)/2.0;

constant vl : real := -ABS(hys)/2.0;

begin

if vin’above(vh) ...