Design Recipes for FPGAs: Using Verilog and VHDL

new package called fp_pkg that as a minimum contains these type

declarations:

package fp_pkg is

type fixsign is array (integer range <>) of std_logic;

subtype fp8_3 is fixsign ( 8 downto -3);

end package;

package body fp_pkg is

end package body;

We can now use this package in a VHDL model by compiling the

package into the current work library and calling the package as

we need it:

Use work.fp_pkg.all;

This will provide access to all the fixed point functions and types

required.

In this library, we have two types of functions. The first type are

required for translating physical types (such as std_logic_vector)

to our new types and vice versa. These are important ...