Design Recipes for FPGAs: Using Verilog and VHDL

15

Behavioral Modeling in VHDL

Introduction

There is a real need to abstract to a higher level in many designs to

make the overall system level design easier. There is less need to

worry about details of implementation at the system level if the

design can be expressed behaviorally, especially if the synthesis

method can handle any clock, partitioning or implementation

issues automatically.

Furthermore, by using system level, or behavioral, analysis,

decisions can be made early in the design process so that poten-

tially costly mistakes can be avoided. Preliminary area and power

estimates can be made and key performance specifications and

architectural decisions can be made using this approach, without

requiring to have detailed designs for every block. ...