Design Recipes for FPGAs: Using Verilog and VHDL

Design Recipes for FPGAs

244

elsif (rising_edge(Clock) and (load = ‘1’)) then

q <= d;

end if;

end process;

end architecture beh;

Notice that although there are four inputs (clk, nrst, load and d),

only clk and nrst are included in the process sensitivity list. If load

and d change, then the process will ignore these changes until the

clk rising edge or nrst goes low. If the load is not used, then the reg-

ister will load the data on every clock rising edge unless the reset is

low. The VHDL for this slightly simpler register is given below:

library ieee;

use ieee.std_logic_1164.all;

entity reg_rst is

port (d, clk, nrst : in std_logic;

q : out std_logic);

end entity ...