Design Recipes for FPGAs: Using Verilog and VHDL

Design Recipes for FPGAs

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decrypt_shift_distance(round));

end if;

return result;

end;

The key_rotate function simply calls the above function twice:

function key_rotate

--moods inline

(key : in vec56;

round : natural range 0 to 15;

encrypt : std_logic)

return vec56 is

begin

return do_rotate(key(1 to 28),round,encrypt) &

do_rotate(key(29 to 56),round,encrypt);

end;

Finally, the key compression function key_compress selects 48

of the 56 bits to pass to the S-block algorithm:

function key_compress(key : in vec56) return vec48 is

--moods inline

begin

return

key(14) & key(17) & key(11) & key(24) &

...

key(50) & key(36) & key(29) & key(32);

end;

Initial synthesis

The design ...