Design Recipes for FPGAs: Using Verilog and VHDL

Design Optimization

187

This implementation requires 3 adders and takes 3 cycles to get

the answer. If we were more systematic with the same resources,

we could reduce this to two cycles by adopting a different struc-

ture shown in Figure 44.

This is a classic case of an expression tree being reduced so

that the control path can take fewer cycles, but achieving the

same data path result. We could also the visage the case where

we only use a single addition block, but use registers to store

the intermediate sums and then ‘pipeline’ the sums until we com-

plete the expression. This would potentially take the longest,

however would result in the smallest ...