IBM eServer zSeries 900 Technical Guide

Book description

This edition of the IBM eServer zSeries 900 Technical Guide contains additional and updated information on the following topics:
New 16 Turbo models
Customer Initiated Upgrade (CIU) support
Concurrent memory upgrades
Concurrent undo Capacity BackUp (CBU)
OSA-E High Speed Token Ring support
OSA-Express enhancements
Enhanced IBM PCI Cryptographic Accelerator (PCICA) for security
Customer-defined UDXs
FICON Express channel cards, CTC support, Cascading Directors support, 2Gbit/sec links
Fibre Channel Protocol (FCP) support for SCSI devices
HiperSockets support
Intelligent Resource Director (IRD) LPAR CPU Management support for non-z/OS logical partitions
System Managed Coupling Facility Structure Duplexing
Message Time Ordering for Parallel Sysplex
64-bit support for Coupling Facility
RMF support for PCICA, PCICC, and CCF
RMF reporting on System Assist Processor (SAP)
Note that a chapter containing information on connectivity has been added to this edition, as well as a new appendix describing fiber cabling services.
This IBM Redbooks publication is intended for IBM systems engineers, consultants, and customers who need the latest information on z900 features, functions, availability, and services.

Table of contents

  1. Notices
    1. Trademarks
  2. Preface
    1. The team that wrote the second edition
    2. The team that wrote the first edition
    3. Notice
    4. Comments welcome
  3. Chapter 1: zSeries 900 overview
    1. Introduction
    2. z900 family models
    3. System functions and features
      1. Processor
      2. Memory
      3. I/O connectivity
      4. Cryptographic coprocessors
      5. Parallel Sysplex support
      6. Intelligent Resource Director
      7. Workload License Charge
      8. Hardware consoles
    4. Concurrent upgrades
    5. 64-bit z/Architecture
    6. z900 Support for Linux
    7. Autonomic Computing
  4. Chapter 2: zSeries 900 system structure
    1. Design highlights
    2. System design
      1. 20-PU system structure
      2. 12-PU system structure
      3. Processing units
      4. Reserved Processors
      5. Processing Unit assignments
      6. Processing Unit sparing
    3. Modes of operation
      1. Basic Mode
      2. Logically Partitioned Mode
    4. Model configurations
      1. General purpose models
      2. Capacity models
      3. Coupling Facility model
      4. Hardware Management Console
      5. Frames
      6. CPC cage
      7. MultiChip Module design
      8. PU design
    5. Memory
      1. Memory configurations
      2. Storage operations
      3. Reserved storage
      4. LPAR storage granularity
      5. LPAR Dynamic Storage Reconfiguration
    6. Channel Subsystem
      1. Channel Subsystem overview
      2. Channel Subsystem operations
      3. Channel Subsystem structure
      4. Self Timed Interfaces
      5. I/O cages
      6. Channels to SAP assignment
      7. Channel feature cards
  5. Chapter 3: Connectivity
    1. Connectivity overview
      1. Configuration planning
      2. Channel features support
      3. CHPID assignments
      4. HiperSockets (iQDIO) and Internal Coupling-3 (IC-3) channel definitions
      5. Enhanced Multiple Image Facility
      6. Channel planning for availability
      7. Configuration guidelines and recommendations
    2. Parallel channel
      1. Connectivity
    3. ESCON channel
      1. Connectivity
    4. Fibre Connection channel
      1. Description (1/2)
      2. Description (2/2)
      3. Connectivity (1/2)
      4. Connectivity (2/2)
      5. Migrating from ESCON to FICON connectivity
      6. FICON distance solutions
    5. FICON channel in Fibre Channel Protocol (FCP) mode (1/2)
    6. FICON channel in Fibre Channel Protocol (FCP) mode (2/2)
      1. Connectivity
    7. Open Systems Adapter-2 channel
      1. Connectivity
    8. OSA-Express channel (1/2)
    9. OSA-Express channel (2/2)
      1. Connectivity
    10. External Time Reference
      1. Connectivity
    11. Parallel Sysplex channels
      1. Connectivity (1/2)
      2. Connectivity (2/2)
    12. HiperSockets
      1. Connectivity
  6. Chapter 4: Cryptography
    1. Cryptographic function support
    2. Cryptographic hardware features
      1. z900 cryptographic feature codes
      2. Cryptographic Coprocessor (CCF) standard feature
      3. PCI Cryptographic Coprocessor (PCICC) feature
      4. PCI Cryptographic Accelerator (PCICA) feature
    3. Cryptographic RMF monitoring
    4. Software Corequisites
    5. Certification
    6. References
  7. Chapter 5: Sysplex functions
    1. Parallel Sysplex
      1. Parallel Sysplex described
      2. Parallel Sysplex summary
    2. Coupling Facility support
      1. Coupling Facility Control Code (CFCC)
      2. Model 100 Coupling Facility
      3. Operating system to CF connectivity
      4. ICF processor assignments
      5. Dynamic CF dispatching and dynamic ICF expansion
    3. System-managed CF structure duplexing
      1. Benefits
      2. Solution
      3. Configuration planning
    4. Geographically Dispersed Parallel Sysplex
      1. GDPS/PPRC
      2. GDPS/XRC
      3. GDPS and z900 features
    5. Intelligent Resource Director
      1. IRD overview
      2. LPAR CPU management
      3. Dynamic Channel Path Management
      4. Channel Subsystem Priority Queueing
      5. WLM and Channel Subsystem priority
      6. Special considerations and restrictions
      7. References
  8. Chapter 6: Capacity upgrades
    1. Concurrent upgrades
    2. Capacity Upgrade on Demand (CUoD)
    3. Customer Initiated Upgrade (CIU)
    4. Capacity BackUp (CBU)
    5. Nondisruptive upgrades
      1. Upgrade scenarios
      2. Planning for nondisruptive upgrades
  9. Chapter 7: Software support
    1. Operating system support
    2. z/OS and OS/390
    3. z/VM and VM/ESA
    4. Linux
    5. VSE/ESA
    6. TPF
    7. 64-bit addressing OS considerations
    8. Migration considerations
      1. Software and hardware requirements
      2. Considerations after concurrent upgrades
    9. Workload License Charges
  10. Appendix A: Reliability, availability, and serviceability functions
    1. RAS concepts
    2. RAS functions of the processor
    3. RAS functions of the memory
    4. RAS functions of the I/O
    5. Other RAS enhancements
  11. Appendix B: Hardware Management Console and Support Element
    1. Hardware Management Console (HMC)
    2. Support Elements (1/2)
    3. Support Elements (2/2)
    4. HMC to SE connectivity
    5. Remote operations (1/2)
    6. Remote operations (2/2)
    7. HMC and SE functions
  12. Appendix C: z900 upgrade paths
    1. Vertical upgrade paths within z900
    2. Horizontal upgrade paths from S/390 G5/G6 to z900
    3. Upgrade paths for z900 Coupling Facility model
  13. Appendix D: Resource Link
  14. Appendix E: CHPID Mapping Tool
  15. Appendix F: Environmental requirements
    1. Server dimensions - plan view
    2. Shipping specifications
    3. Power requirements
  16. Appendix G: Fiber cabling services
    1. Fiber connectivity solution options
    2. zSeries Fiber Cabling Service for z800 and z900
    3. Fiber Transport Services (FTS) (1/2)
    4. Fiber Transport Services (FTS) (2/2)
  17. Glossary (1/2)
  18. Glossary (2/2)
  19. Related publications
    1. IBM Redbooks
      1. Other resources
    2. Referenced Web sites
    3. How to get IBM Redbooks
      1. IBM Redbooks collections
  20. Index (1/2)
  21. Index (2/2)
  22. Back cover

Product information

  • Title: IBM eServer zSeries 900 Technical Guide
  • Author(s): Franck Injey
  • Release date: September 2002
  • Publisher(s): IBM Redbooks
  • ISBN: None