Semiconductors

IC DfM for Devices and Products 121

values. Such ow combines post-OPC layout back-annotation and selective

extraction from the global circuit netlist. Pin slacks of critical instances may

be worsened on average if more critical cells and cell types become involved

on critical paths.

Having located critical layout patterns across the full chip, where OPC could

not achieve the desired L

gate

control, a calibrated OPC algorithm should be

applied locally to attain savings on full-chip OPC runtime, such as in designs

with matching transistors (e.g., mixed signal or clock generation in micropro-

cessors) as a supplement to multithreshold voltage assignments, or gate sizing.

OPC compensation for CD distortions becomes a major source of system- ...