Semiconductors

196 Semiconductors: Integrated Circuit Design for Manufacturability

the 100-mV noise margins or gain variations. These designs can use densely

packed layout at the expense of accurate matching. But for similar output for

RF designs operating in the frequency range of 100 GHz, the phase noise can

make it impossible to realize analog blocks (e.g., the phase-locked loops). The

sensitivity of operational ampliers at the microvolt level requires parasitics

simulation of all building blocks of the circuit. While digital design rules are

still used in the verication, the unaccounted-for variation in parasitic capac-

itance and resistance can be abov ...