September 2018
Intermediate to advanced
248 pages
8h 19m
English
Content preview from Semiconductors
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174 Semiconductors: Integrated Circuit Design for Manufacturability
of current 193-nm water immersion lithography toward the 22-nm node,
double-pat terning lithography is a promising option when contrasted to EUV
(Table4.6) It makes the k
1
factor no longer relevant, bypassing its theoretical
limit of 0.25 by breaking down the different contributions to CD uniformity
(CDU) and overlay. Beyond processes for memory products, lithographic
patterning capability needs resolution better than that of ArF water-based
immersion tools, even when approaching the practical limit of NA = 1.35.
DPIL (double pattern immerssion lithography ...
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