Semiconductors

184 Semiconductors: Integrated Circuit Design for Manufacturability

dielectric etching replaces metal-etch as the critical step that denes the

spacing of the interconnect lines, while the task of planarization moves to

the metal deposition and CMP.

During the CMP of patterned copper wafers, copper dishing and SiO

2

erosion lead to deviations from the at surface, during the overpolish step to

ensure complete copper removal across the entire wafer (Figure4.11).

Copper dishing is measured as the difference in height between the center

of the copper line (i.e., the lowest point of the dish) and the point where the

SiO

2

levels ...