Cost Considerations for Three-Dimensional Integration*
Abstract
Cost issues for vertical integration are discussed in this chapter. The diverse steps introduced in each of the manufacturing processes for through silicon vias (TSVs) result in different cost requirements. These steps include, for example, TSV etching, lithography, liner processing, barrier and copper (Cu) seed processing, metal plating, surface polishing, and backside processing. Models that capture these cost implications are provided. Other relevant aspects, such as the area of the active die and prebond test coverage, are included in these models. Cost models for interposer-based (2.5-D) systems are also discussed, including redistribution layers, metal–insulator–metal ...
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