Timing Optimization for Two-Terminal Interconnects*
Abstract
The task of timing driven placement of the through silicon vias (TSVs) in a three-dimensional (3-D) circuit is considered in this chapter. Due to the different impedance characteristics of the horizontal interconnects and TSVs the interconnect delay can be greatly affected by the placement of the TSVs. A method for optimally placing one TSV within point-to-point intertier nets is presented. This method is extended to point-to-point nets that contain several TSVs. Near-optimal heuristics are provided to solve this problem. Based on the Elmore delay, low complexity algorithms are described to place the TSVs. These algorithms are applied to several example 3-D circuits with multiple ...
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