May 2024
Intermediate to advanced
889 pages
30h 8m
English
book
The X 86 Microprocessors: Architecture, Programming and Interfacing (8086 to Pentium) 2nd Edition by Pearson
by Lyla B. Das
Content preview from The X 86 Microprocessors: Architecture, Programming and Interfacing (8086 to Pentium) 2nd Edition by Pearson
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10-40
THE
x86 MICROPROCESSORS
To know the current mask status, OCW1 can be read. For example, to mask the interrupt
requests on IR0, IR3 and IR7, OCW1 has to have the value
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 0 0 1 0 0 1
i.e., 89H
Example 10.20
Write instructions to read the current status of the IMR. After that, change the masking
structure such that only IR0 is masked.
Solution
The status of the IMR is to be read. Read the status of OCW1. The instruction is
IN AL, 0C2H ;C2H is the address we have used in
Example 10.19 and it is the same as that of
ICW2 (with A0 = 1)
MOV AL, 01 ;mask bit for IR0 is set
MOV BL, AL
OUT 0C2H, AL ;send to OCW1 ...
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