May 2024
Intermediate to advanced
889 pages
30h 8m
English
book
The X 86 Microprocessors: Architecture, Programming and Interfacing (8086 to Pentium) 2nd Edition by Pearson
by Lyla B. Das
Content preview from The X 86 Microprocessors: Architecture, Programming and Interfacing (8086 to Pentium) 2nd Edition by Pearson
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7-12
THE
x86 MICROPROCESSORS
7.3 | Memory Banks
8086 has a 16-bit memory bus – which means that data transfer can occur at a maximum
rate of 16 bits (one word) per bus cycle. However, sometimes, only a byte needs to be
accessed. This means that the processor must have both options – i.e., both byte and
word transfer must be possible. We know that for a word transfer two byte locations must
be accessed; i.e., two addresses are actually needed.
Keeping these concepts in mind, let us see how memory is organized for 8086. A
16-bit data can be obtained by accessing two memory chips in parallel, each having
8 bits each of the word (see Fig. 7.11). ...
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