The X 86 Microprocessors: Architecture, Programming and Interfacing (8086 to Pentium) 2nd Edition by Pearson

6-18

THE

x86 MICROPROCESSORS

iii) Assert the write control signal which is part of the control bus.

iv) Wait until the data is stored in the addressed location.

v) De-activate the memory write signal. This ends the memory write operation.

For the 8086, the control signals for a write machine cycle are the same as in a READ

cycle except the WR is used in place of RD . Also, the DT / R signal will be high (for

‘data transmit’) for writing. This being the case, the complete write machine cycle

is not shown here; only the timing of placing of the address and data on the buses and

the lowering of the write control signal are shown here. See F ...