May 2024
Intermediate to advanced
889 pages
30h 8m
English
book
The X 86 Microprocessors: Architecture, Programming and Interfacing (8086 to Pentium) 2nd Edition by Pearson
by Lyla B. Das
Content preview from The X 86 Microprocessors: Architecture, Programming and Interfacing (8086 to Pentium) 2nd Edition by Pearson
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SEMICONDUCTOR MEMORY DEVICES 12-23
L2 cache on motherboards now became L3 cache when used with microproces-
sors containing built-in L2 caches. However, the latest is that with more CPUs
becoming ‘multicore’ (refer Section 16.7.2) a tertiary level cache was added on
to the CPU die, called the L3. It also became common to have the three levels be
larger in size than the next lower level, so that it became not uncommon to find Level 3
cache sizes of eight megabytes. This trend appears to continue for the foreseeable future.
Figure 12.16 shows three leads of cache for the latest x86 processors. This is only
schematic, and the arrows do not show the ...
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