This means that the hardware for VLIWs is much less complex, but the compiler
has to be very smart; further, it should be an optimized compiler that knows all about
the processor’s microarchitecture, ISA, etc. It must be able to take a stream of sequential
instructions and convert it to an instruction word. This instruction word is presented to
many different functional units for concurrent execution.
The idea seems quite simple, but the compiler needs to be updated for each new
VLIW architecture. This is one major drawback for them. The other major drawback is
that it might not be possible always to find sufficient ...
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