May 2024
Intermediate to advanced
889 pages
30h 8m
English
book
The X 86 Microprocessors: Architecture, Programming and Interfacing (8086 to Pentium) 2nd Edition by Pearson
by Lyla B. Das
Content preview from The X 86 Microprocessors: Architecture, Programming and Interfacing (8086 to Pentium) 2nd Edition by Pearson
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PERIPHERAL INTERFACING–II 10-43
IN AL, 0C0H ;read IRR
MOV BL, AL ;save IRR in BL
MOV AL, 69H ;write OCW3 for reading ISR
IN AL, 0C0H ;read ISR
MOV CL, AL ;save it in CL
Note The 8259 is a complex chip, and for finer details, the data sheet of the chip is to
be referred to.
10.4 | Cascade Mode
The 8259 can be easily interconnected in a system of one master with up to eight slaves
to handle up to 64 priority levels. The master controls the slaves through the 3 line cas-
cade bus. The cascade bus acts like chip selects to the slaves during the INTA sequence.
In a cascade configuration, the slave interrupt outputs are connected to the master ...
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