Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

12

MULTIPLIERS

According to speed/cost requirements, the technology at hand, and a number of other circumstantial criteria, such as expandability, user-configurable features, copy protection, or power consumption, a great quantity of theoretical and practical multiplier implementations have been proposed in the literature. This chapter presents classic multipliers in base B with emphasis on base 2. In particular, attention is paid to multiplication array multipliers and adding tree reduction techniques. Based on the extended-Booth representation, the Per Gelosia multiplier is described as a particular multiplication array for signed-digit numbers. Some typical FPGA implementations are presented.

As a matter of fact, combinational multipliers are inherently faster, although generally less cost effective, than their corresponding (same algorithm) sequential implementation. The cost criterion is to be taken in a general theoretical context of hardware consumption, not directly related to the money price; it is well known that the price is more related to the batch size of production than to the gate cost itself. As mentioned in Chapter 9, PLA integrated circuit (IC) technology is a good example of inexpensive mass production; FPGA, for its reusability feature, may be considered cheap whenever it is used for special (low-quantity requirement) circuit design or simply for prototype design.