March 2006
Intermediate to advanced
576 pages
11h 43m
English
book
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
by Jean-Pierre Deschamps, Gery J.A. Bioul, Gustavo D. Sutter
Content preview from Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
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5.4 BIBLIOGRAPHY
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[DAD1965] L. Dadda, Some schemes for parallel multipliers. Alta Frequenza 34: 349–356 (1965).
[DAV1977] M. Davio and G. Bioul, Fast parallel multiplication. Philips Res. Rpts. 32: 44–70 (1977).
[KOR1993] I. Koren, Computer Arithmetic Algorithms, Prentice Hall, Englewood Cliffs, NJ, 1993.
[MAS1990] M. Nagamatsu, et al., A 15-ns 32 × 32-b CMOS multiplier with an improved parallel structure. IEEE J. Solid-State Circuits 25(2): 494–499 (1990).
[OBE1964] S. F. Oberman and M. Flynn, Advanced Computer Arithmetic Design, Wiley-Interscience, Hoboken, NJ, 2001.
[OKL1996] V. G. Oklobdzija, D. Villeger, and S. S. Liu, A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach. IEEE Trans. Comput. 45(3): 294–305 (1996).
[PAR1999] Behrooz Parhami, Computer Arithmetic, Algorithms and Hardware Designs, Oxford University Press, New York, 1999.
[WAN1995] Z. Wang, G. A. Jullien, and W. C. Miller, A new design technique for column compression multipliers. IEEE Trans. Comput. 44(8): 962–970 (1995).
[WAL1964] C. S. Wallace, A suggestion for fast multipliers. IEEE Trans. Electron. Comput. EC-13(Feb): 14–17 (1964).
Synthesis of Arithmetic Circuits: FPGA, ASIC, and Embedded ...