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Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
book

Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

by Jean-Pierre Deschamps, Gery J.A. Bioul, Gustavo D. Sutter
March 2006
Intermediate to advanced
576 pages
11h 43m
English
Wiley-Interscience
Content preview from Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

1.4 HARDWARE–SOFTWARE PARTITIONING

The hardware–software partitioning consists of deciding which operations will be executed by the central processing unit (the software) and which ones by specific coprocessors (the hardware). As a matter of fact, the platform selection and the hardware–software partitioning are tightly related operations. For systems requiring little data processing capability, the whole system is implemented in software. If higher performances are necessary, the noncritical operations, as well as control of the operation sequence, are executed by the central processing unit, while the critical ones are implemented within specific coprocessors.

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