Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

14.3 LOGARITHM OPERATOR

This section presents an implementation for binary logarithms computation using multiplicative normalization. As shown in Section 7.3.3.1, the main (logarithm) sequence may be computed in another base different from the auxiliary sequence, built up in binary. The implementation, displayed in Figure 14.17, handles all data and results in binary. Algorithm 7.8 (logarithm computation by multiplicative normalization) assumes that the numerical values of (1 + 2⁻ⁱ), (1 − 2⁻ⁱ), ln (1 + 2⁻ⁱ), and ln (1 − 2⁻ⁱ) are available. In practical implementations, those values are read out from a look-up table to be preset by the designer. As the precision of the result is linear (1 bit-result per step), then, for p-bit precision, 2p logarithms ln (1 ± 2⁻ⁱ) and 2p values (1 ± 2⁻ⁱ) have to be precomputed and loaded. On the other hand, the precision of the stored values has to be defined too: if p is the required precision for the result, at least p bits are needed per LUT entry. Actually, to cope with the errors generated by rounding and error propagation, some more bits have to be included. Nevertheless, 4p² is a fair order of magnitude of the LUT cost. The argument X is in [1/2, 2].

A counter, not represented in the circuit displayed in figure 14.17, may be used to increment step number i. LUT outputs are thus updated while, at the same time, a combinational circuit computes x_−i(i) and x_−i(i).not x_−i−1(i). During the second phase of step i, the registers X and acc are loaded ...