March 2006
Intermediate to advanced
576 pages
11h 43m
English
book
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
by Jean-Pierre Deschamps, Gery J.A. Bioul, Gustavo D. Sutter
Content preview from Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
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11.3 BIBLIOGRAPHY
[BIO2003] G. Bioul, J.-P. Deschamps, and G. Sutter, Efficient FPGA implementation of carry-skip adders. In: Proceedings of the 3rd Reconf. Computing and Applications (JCRA 03), UAM, Madrid, Sept. 2003, pp. 81–90.
[BRE1982] R. Brent and H. T. Kung, A regular layout for parallel adders. IEEE Trans.Comput., C-31(3): 260–264 (1982).
[HAN1987] T. Han and D. A. Carlson, Fast area-efficient VLSI adders. In: Proceedings of the 8th Symposium on Computer Arithmetic, 1987, pp. 49–56.
[KOG1973] P. M. Kogge and H. S. Stone, A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Trans. Comput., C-22(8), 786–793 (1973).
[LAD1980] R. E. Ladner and M. J. Fischer, Parallel prefix computation. J. ACM 27: 831–838 (1980).
[SUG1990] B. Sugla and D. Carlson, Extreme area-time tradeoffs in VLSI. IEEE Trans. Comput., 39(2), 251–257 (1990).
Synthesis of Arithmetic Circuits: FPGA, ASIC, and Embedded SystemsBy Jean-Pierre Deschamps, Géry J. A. Bioul, and Gustavo D. SutterCopyright © 2006 John Wiley & Sons, Inc.