Embedded Systems Design, 2nd Edition

358 Embedded systems design

• There are no data dependencies outstanding

This leads on from the previous discussion and concerns

the ability of an instruction to immediately use the result

from a previous instruction. In many cases, this is only

permitted if there is a delay to allow the processor to

synchronise itself. As a result, the single cycle delay has the

same result as a single cycle wait state and thus the perform-

ance is degraded.

As a result of all these conditions, it should not be assumed

that a 80 MHz single cycle instruction processor such as a DSP- or

a RISC- based machine can provide 80 MIPs of processing power.

It can provided the conditions ...