Embedded Systems Design, 2nd Edition

130 Embedded systems design

Latching DA2 and DA3 holds the address valid while

allowing the modulo 4 counter to propagate the next value through.

The falling edge of BCLK* is then used to gate the read/write

signal to create a write pulse. The write pulse is removed before

the next address is latched. This guarantees that the write pulse

will be generated after the address has become valid. This circuit

neatly solves the competing criteria of bringing the write pulse

high before the address can be changed and the need to change the

address as early as possible

The table shows the timing and the values for the write

pulse, t

WLWH

, write data set-up time, ...