Embedded Systems Design, 2nd Edition

Interrupts and exceptions 209

This problem can be contained by declaring exception

routines and data as non-cachable, or through the use of a BATC

or transparent window to remove the page fault and table walk.

These techniques couple the CPU directly to external memory

which, if slow, can be extremely detrimental to performance.

Small areas of very fast memory can be reserved for exception

handling to solve this problem; locking routines in cache can also

be solutions, at the expense of performance in other system

functions. It should be of no surprise that many of today's RISC

controllers are using local memory (tightly coupled memory or

TCM) to store ...