Embedded Systems Design, 2nd Edition

Memory systems 117

The movement from one state is governed by memory

actions, cache hits and misses and snooping activity. For example,

if a processor needs to write data to a memory address that has a

write-back policy and cache coherency enabled as part of its page

descriptors — controlled by the WIM bits — and causes a cache

miss, the processor will move from an invalid state to a modified

state by performing a ‘read with intent to modify’ bus cycle.

The MESI protocol is widely used in multiprocessor de-

signs, for example, in the Futurebus+ interconnection bus. The

MPC601 uses this protocol.

The MEI protocol

The MEI protocol — modified, exclusive, invalid ...