Embedded Systems Design, 2nd Edition

360 Embedded systems design

dependency and thus can carry on processing. The storage in-

struction S0 has to wait one cycle until F0 has completed and

similarly the fetch instruction F2 must wait until S0 has finished.

These delays are still there because of the common resource that

the store and fetch instructions use, i.e. the external memory

interface. By reordering in this way, the five instruction sequence

is completed twice in every 20 clocks giving a 100 ns timing which

is a significant improvement.

This example also shows that the task in this case is I/O

bound in that the main delays are caused by waiting for data to be

fetched or stored. The ...