Embedded Systems Design, 2nd Edition

110 Embedded systems design

The usual cache implementation involves adding dirty bits

to the tag to indicate which cache lines or partial lines hold

modified data that has not been written out to the main memory.

This dirty data must be written out if there is any possibility that

the information will be lost. If a cache line is to be replaced as a

result of a cache miss and the line contains dirty data, the dirty data

must be written out before the new cache line can be accepted. This

increases the impact of a cache miss on the system. There can be

further complications if memory management page faults occur.

However, these aspects must be put into perspective ...