October 2002
Intermediate to advanced
430 pages
14h 57m
English
Content preview from Embedded Systems Design, 2nd Edition
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Embedded processors 41
registers to be replaced by two groups of eight data registers and
eight address registers. All these registers and the program coun-
ter are 32 bits wide.
31 0
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D6
D7
ADDRESS
REGISTERS
DATA
REGISTERS
PROGRAM
COUNTER
CONDITIO
N
CODES
The MC68000 USER programmer’s model
The MC68000 hardware
Address bus
The address bus (signals A1 – A23) is non-multiplexed and
24 bits wide, giving a single linear addressing space of 16 Mbytes.
A0 is not brought out directly but is internally decoded to generate
upper and lower data strobes. This allows the processor to access
either or both the upper and lower bytes that comprise the ...
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