October 2002
Intermediate to advanced
430 pages
14h 57m
English
Content preview from Embedded Systems Design, 2nd Edition
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88 Embedded systems design
DRAM is latched by the processor or bus master. This means that
the next access cannot be started until this has been completed,
causing delays.
EDO memory does not cause the outputs to go to high
impedance and it will continue to drive data even if the CAS*
signal is removed. By doing this, the CAS* precharge can be
started for the next access while the data from the previous access
is being latched. This saves valuable nanoseconds and can mean
the removal of a wait state. With very high performance proces-
sors, this is a big advantage and EDO type DRAM is becoming the
de facto standard for PCs and workstations or any other ...
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