Embedded Systems Design, 2nd Edition

Memory systems 77

or through the use of software. These techniques will be described

in more detail later on in this chapter.

RAS*

CAS*

A0-A9

Dout

Row

address

Column

address

Read

data

Write*

Basic DRAM interface

The basic DRAM interface takes the processor generated

address, places half of the address (the high order bits) onto the

memory address bus to form the row address and asserts the RAS*

signal. This partial address is latched internally by the DRAM. The

remaining half (the low order bits), forming the column address,

are then driven onto the bus and the CAS* signal asserted. After

the access time has expired, the data appears on the Dout pin and

is latched ...