Embedded Systems Design, 2nd Edition

Memory systems 109

Main

memory

Processor

DMA

controller

I/O

bus

Cache

memory

A coherent cache architecture

If there are more than two caches, the stale data problem

reappears in another guise. Consider such a system where two

processors with caches have a copy of a global variable. Neither

processor accesses main memory when reading the variable, as

the data is supplied by the respective caches. Processor A now

modifies the variable — its cache is updated, along with the

system memory. Unfortunately, processor B´s cache is left with

the old stale data, creating a coherency problem. A similar prob-

lem can occur within paging systems.

It also does not address the ...