Embedded Systems Design, 2nd Edition

106 Embedded systems design

If the processor does not invalidate any associated cache entries,

the cache contents will be different from the main memory con-

tents by virtue of the new page that has been swapped in.

Of the two systems, physical caches are more efficient,

providing the cache coherency problem is solved and MMU

delays are kept to a minimum. RISC architectures like the PowerPC

solve the MMU delay issue by coupling the MMU with the cache

system. An MMU translation is performed in conjunction with the

cache look up so that the translation delay overlaps the memory

access and is reduced to zero. This system combines the speed

advantages of a ...