Embedded Systems Design, 2nd Edition

Embedded processors 51

E

X

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A

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INSTRUCTION

CACHE

DATA

CACHE

BUS

CONTROL

CPU

INSTR

PIPE

PMMU

ATC

ADDRESSES

DATA

The MC68030 internal block diagram

The processor supports both the coprocessor interface and

the MC68020 asynchronous bus with its dynamic bus sizing and

misalignment support. However, it has an alternative synchro-

nous bus interface which supports a two–clock access with op-

tional single-cycle bursting. The bus interface choice can be made

dynamically by external hardware.

The MC68040

The MC68040 incorporates separate integer and floating

point units giving sustained performances of 20 integer MIPS and

3.5 double precision Linpack MFLOPS respectively, ...