October 2002
Intermediate to advanced
430 pages
14h 57m
English
Content preview from Embedded Systems Design, 2nd Edition
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62 Embedded systems design
The Stanford RISC model
This model uses a smaller number of registers (typically 32)
and relies on software techniques to allocate register usage during
procedural calls. Instruction execution order is optimised by its
compilers to provide the most efficient way of performing the
software task. This allows pipelined execution units to be used
within the processor design which, in turn, allow more powerful
instructions to be used.
Instruction
queue
Instruction
issue
Floating
point unit
Branch
unit
Integer unit
GPR
file
FPR
file
UTLB
BTLB
Tags 32 kbyte
unified
cache
Processor bus interface
Instruction unit
32 bit address bu
s
64 bit data bus
MMU
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