October 2002
Intermediate to advanced
430 pages
14h 57m
English
Content preview from Embedded Systems Design, 2nd Edition
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
Start your free trial
108 Embedded systems design
PROCESSOR
CACHE
MEMORY
CASE 1:
WRITE-THROUGH
PROCESSOR
CACHE
MEMORY
CASE 2:
WRITE-BACK
(Delayed)
CACHE
MEMORY
CASE 4:
WRITE
BUFFERING
PROCESSOR
CACHE
MEMORY
CASE 3:
NO CACHING
OF WRITE CYCLES
Invalid
PROCESSOR
Different write schemes
Other problems can occur when data that is not intended to
be cached is cached by the system. Shared memory or I/O ports
are two areas that come immediately to mind. Shared memory
relies on the single memory structure to contain the recent data. If
this is cached then any updates may not be made to the shared
memory. Any other CPU or DMA that accesses the shared memory
will not get the latest data and the stale data ...