October 2002
Intermediate to advanced
430 pages
14h 57m
English
Content preview from Embedded Systems Design, 2nd Edition
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Basic peripherals 143
shows such a configuration. If pin 1 on the master MCU is driven
low, slave 1 is selected and so on. The unselected slaves tri-state the
SPI connections and do not receive the clocked data and take no
part in the transfer.
MOSI
MOSO
SCK
Master
MCU
Slave 1 Slave 2
Slave 3
1 2 3
ss
ss ss
Supporting multiple slave devices
It should not be assumed that an implementation buffers
data. As soon as the master writes the data into the SPDR it is
transmitted as there is no buffering. As soon as the byte has been
clocked out, an interrupt is generated indicating that the byte has
been transferred. In addition, the SPIF flag in the status register
(SPSR) ...
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