October 2002
Intermediate to advanced
430 pages
14h 57m
English
Content preview from Embedded Systems Design, 2nd Edition
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Memory systems 103
the caches so far described can be improved by further reorganiz-
ing so that each tag is associated with a line of long words which
can be burst filled using a page memory interface.
…
Tag
Tag0
Tag1
Tag2
Tag15
v0
v0
v0
v0
v1
v1
v1
v1
v2
v2
v2
v2
v3
v3
v3
v3
Data0 Data1 Data2 Data
3
COMPARATOR
Data to
CPU
Cache
hit
Tag
replace
1 of 16
select
Index
Long-word
Select
Access address
The MC68030 direct mapped burst fill cache
The logic behind this idea is based on the sequential nature
of instruction execution and data access. Instruction fetches and
execution simply involve accesses to sequential memory locations
until a program flow change happens due to the execution of ...
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