Embedded Systems Design, 2nd Edition

Embedded processors 59

them concern register sets and usage. They both have a Harvard

external bus architecture consisting of separate buses for instruc-

tions and data. This allows data accesses to be performed in

parallel with instruction fetches and removes any instruction/

data conflict. If these two streams compete for a single bus, any

data fetches stall the instruction flow and prevent the processor

from achieving its single cycle objective. Executing an instruction

on every clock requires an instruction on every clock.

The Berkeley RISC model

The RISC 1 computer implemented in the late 1970s used a

very large register set of 138 × 32 bit registers. ...