Embedded Systems Design, 2nd Edition

142 Embedded systems design

register to receive more bits without losing the data. The FIFO

buffer is read to receive the data hence the acronym’s derivation

— first in, first out. The reverse can be done for the transmitter so

that data can be sent to the transmitter before the previous value

has been sent.

The size of the FIFO buffer is important in reducing proces-

sor overhead and increasing the serial port’s throughput as will be

explained in more detail later on. The diagram shows a generic

implementation of a serial interface between a processor and

peripheral. It uses a single clock signal which is used to clock the

shift registers in each transmitter ...