Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

3.8 TIMING DIAGRAM

A timing diagram is the graphical representation of input and output signals as functions of time. Since the inputs and outputs can only take the values 0 or 1, their graphical representations are series of square pulses with a variety of time lengths. The inputs and outputs are drawn on the same diagram to show the input-output behavior of the digital system. A timing diagram is usually generated by an oscilloscope or logic analyzer. Computer-aided design tools have software simulator that generate timing diagrams. A timing diagram shows all possible input and output patterns, not necessarily in an order similar to that of a truth table.

Consider the timing diagram in Figure 3.8. Notice that the time intervals are equally separated. Notice also that the output transitions do not occur at exactly the same time that the input transitions occur, but a very short time later. The delay in the output transitions, referred to as the propagation delay, is the time difference between the time of input application and the time when the outputs become valid. The propagation delay is a real physical effect of electronic components that make a logic gate or a circuit. Timing diagrams should show propagation delays. However, during the initial design of a logic circuit, the actual circuit components are not well defined, and therefore any propagation delay can only be estimated. Propagation delays are explored further in Chapter 5.